1. Field of the Invention
This application relates generally to image sensor readout chains, which includes sample-and-hold circuits. More specifically, this application relates to an image sensor readout circuit that implements analog gain to improve noise performance and maintain dynamic range.
2. Description of Related Art
Image sensing devices typically consist of an image sensor, generally an array of pixel circuits, as well as signal processing circuitry and any associated control or timing circuitry. Within the image sensor itself, charge is collected in a photoelectric conversion device of the pixel circuit as a result of the impingement of light.
One example of a pixel circuit is illustrated in FIG. 1. As shown in FIG. 1, a pixel circuit 100 includes a photoelectric conversion device 101 (for example, a photodiode), a floating diffusion FD, a transfer transistor 102, a reset transistor 103, an amplification transistor 104, and a selection transistor 105, and a vertical signal line 106. As illustrated, vertical signal line 106 is common to a plurality of pixel circuits within the same column. Alternatively, a vertical signal line may be shared among multiple columns. Gate electrodes of transfer transistor 102, reset transistor 103, and selection transistor 105 receive signals TRG, RST, and SEL, respectively. These signals may, for example, be provided by the control or timing circuitry.
While FIG. 1 illustrates a pixel circuit having four transistors in a particular configuration, the current disclosure is not so limited and may apply to a pixel circuit having fewer or more transistors as well as other elements, such as capacitors, resistors, and the like. Additionally, the current disclosure may be extended to configurations where one or more transistors are shared among multiple photoelectric conversion devices.
The voltage at signal line 106 is measured at two different times under the control of timing circuits and switches, which results in a reset signal (“P-phase value”) and light-exposed or data signal (“D-phase value”) of the pixel. This process is referred to as a correlated double sampling (CDS) method. The reset signal is then subtracted from the data signal to produce a value which is representative of an accumulated charge in the pixel, and thus the amount of light shining on the pixel. The accumulated charge is then converted to a digital value. Such a conversion typically requires several circuit components such as sample-and-hold (S/H) circuits, analog-to-digital converters (ADC), and timing and control circuits, with each circuit component serving a purpose in the conversion. For example, the purpose of the S/H circuit may be to sample the analog signals from different time phases of the photo diode operation, after which the analog signals may be converted to digital form by the ADC. A single-slope ADC is illustrated in FIG. 1, including a comparator 110, a digital counter 120, and a ramp reference voltage Vramp. In FIG. 1, an analog sample and hold circuit is not included, and the sampling of the signal is done digitally by the ramp ADC.
FIG. 2 illustrates a waveform and timing diagram for the different timing phases in acquiring the reset and data signals from a pixel, as well as an example of the voltage VSL during different phases. In FIG. 2, the solid line illustrates a VSL signal when the incoming illumination is at a comparatively low level, whereas the dashed line illustrates a VSL signal when the incoming illumination is at a comparatively high level, where both high and low are within the normal operation level of the pixel under suitable exposure control. As illustrated, the voltage VSL is a result of the photodiode collecting negative charges when it is exposed to light. The reset value is not affected by the incoming illumination when the illumination is within the normal range of pixel operation. That is, the reset value is the same whether the illumination is high or low within this range of operation. The data value, on the other hand, does show a difference, where the data signal level is lower when the illumination is stronger.
As illustrated by FIG. 2, VSL settles to a steady voltage after the pixel has been reset. Then, in the above example where a single-slope ADC is used, the ADC measures the voltage VSL beginning with the start of the reset settling followed by the “ADC of reset signal” period. During this measurement, Vramp begins at a high level and then decreases linearly as a function of time from this initial high level. Simultaneously, the digital counter starts counting from zero while monitoring the output of the comparator so as to stop counting when the comparator changes state. At this point, the stopped count value is a digital value corresponding to the reset signal of the pixel. The data signal value of the pixel is then measured in a similar fashion after the signal line VSL has once again settled; i.e., during the “data noise integration” period illustrated in FIG. 2. The difference between the data and reset values is then interpreted as the amount of illumination on the pixel.
In many practical pixel readout circuits, there is a tradeoff between ADC noise floor and ADC maximum input level. In order to best sense the pixels with low illumination, the readout chain is preferably set to provide high signal gain with lowest input referred noise. At strong illumination, on the other hand, the readout chain is preferably set to provide low signal gain in order not to have saturation. In other words, the preferred settings for low illumination pixels and high illumination pixels are different.
In summary, common attempts to improve noise performance may reduce the dynamic range of the image sensor. Thus, there exists a need for a pixel readout chain that improves the signal-to-noise ratio (SNR) without degrading the dynamic range of the image sensor.